Integrated circuit (IC) chips are often electrically connected by wires (e.g., gold or aluminum wires) to a package substrate in a packaging assembly to provide external signal exchange. Such wires are typically wire bonded to bond pads formed on an IC chip using thermal compression and/or ultrasonic vibration. Wire bonding processes exert thermal and mechanical stresses on the bond pads and on the underlying layers and structure below the bond pads. The structures of the bond pads need to be able to sustain these stresses to ensure a quality bonding of the wires.
Currently, many processes use low-k and ultra low-k dielectric materials in inter-metal dielectric (IMD) layers to reduce RC delay and parasitic capacitances. The general trend in IMD designs is that the dielectric constant (k) of the IMD layers tends to decrease from low-k regime to ultra low-k regime. This, however, means that the IMD layers, in which metal lines and vias are formed, are more mechanically fragile. Further, the IMD layers may delaminate when under the stress applied by the wire bonding force. New bonding structures and methods are thus needed so that the IMD layers are not damaged, while at the same time the benefit of reduced RC delay resulting from the reduced k value is preserved.